interesting. i didn't even think that could be the reason. i thought it might have been something that somehow went missing on the schematic. if that's the way it's supposed to then, awesome. it looks like a neat circuit, i really wonder how it sounds.
Interesting schem, but Q1 and Q4 look a bit odd as if the pots will twiddle the bias of the transistors, and one would normally see a cap between the tone pot and base/base resistors though I have seen that sort of thing with JFETs. About to breadboard it, so we'll see what happens
I just noticed on Q1 the 1UF cap should be connected to Base(rowG) instead of Collector (rowF)
and the 470k should be connected to Collector (rowF) instead of Base (rowG) according to the schematic.
Don,t know how to get the 8.2k connected to Base (rowG) instead of Collector (rowF) from rowA?
I hope this helps i haven't built this yet but plan to soon.Verry sorry if i'm mistaken I always set up schematic next too the vero layout and study them befor i build.I'm still trying to learn more about how these circuits work.Thank you for your time and hard work on your layouts I very much appriciate everyones contributions on here.I'm slowly but surely learning